//rom模块
// module rom(
//            input wire [31: 0] inst_addr_i,
//            output reg [31: 0] inst_o
//        );
//4096个32bitrom空间
//rom设计为每8Bit放一个地址，4个为一个指令，传入的为指令首地址
//这里为32bit为一个地址
// reg [31: 0] rom_mem[4095: 0];

// always@( * )
// 	begin
// 		inst_o = rom_mem[inst_addr_i >> 2];
// 	end
// endmodule


module rom(
           input wire clk,
           input wire rst,
           input wire wen,  //写使能
           input wire [31: 0] w_addr_i,
           input wire [31: 0] w_data_i,
           input wire ren,  //读使能
           input wire [31: 0] r_addr_i,
           output wire [31: 0] r_data_o
       );
wire [11: 0] w_addr = w_addr_i[13: 2];
wire [11: 0] r_addr = r_addr_i[13: 2];

dual_ram#(
            .DW ( 32 ),
            .AW ( 12 ),
            .MEM_NUM ( 4096 )
        )u_dual_ram(
            .clk ( clk ),
            .rst ( rst ),
            .w_en ( wen ),
            .w_addr_i ( w_addr ),
            .w_data_i ( w_data_i ),
            .r_en ( ren ),
            .r_addr_i ( r_addr ),
            .r_data_o ( r_data_o )
        );

endmodule
